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Espressif Systems /ESP32-P4 /I3C_MST /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_DATA_BUF_THLD_INT_ST)TX_DATA_BUF_THLD_INT_ST 0 (RX_DATA_BUF_THLD_INT_ST)RX_DATA_BUF_THLD_INT_ST 0 (IBI_STATUS_THLD_INT_ST)IBI_STATUS_THLD_INT_ST 0 (CMD_BUF_EMPTY_THLD_INT_ST)CMD_BUF_EMPTY_THLD_INT_ST 0 (RESP_READY_INT_ST)RESP_READY_INT_ST 0 (NXT_CMD_REQ_ERR_INT_ST)NXT_CMD_REQ_ERR_INT_ST 0 (TRANSFER_ERR_INT_ST)TRANSFER_ERR_INT_ST 0 (TRANSFER_COMPLETE_INT_ST)TRANSFER_COMPLETE_INT_ST 0 (COMMAND_DONE_INT_ST)COMMAND_DONE_INT_ST 0 (DETECT_START_INT_ST)DETECT_START_INT_ST 0 (RESP_BUF_OVF_INT_ST)RESP_BUF_OVF_INT_ST 0 (IBI_DATA_BUF_OVF_INT_ST)IBI_DATA_BUF_OVF_INT_ST 0 (IBI_STATUS_BUF_OVF_INT_ST)IBI_STATUS_BUF_OVF_INT_ST 0 (IBI_HANDLE_DONE_INT_ST)IBI_HANDLE_DONE_INT_ST 0 (IBI_DETECT_INT_ST)IBI_DETECT_INT_ST 0 (CMD_CCC_MISMATCH_INT_ST)CMD_CCC_MISMATCH_INT_ST

Description

NA

Fields

TX_DATA_BUF_THLD_INT_ST

This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value.
RX_DATA_BUF_THLD_INT_ST

This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value.
IBI_STATUS_THLD_INT_ST

Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value.
CMD_BUF_EMPTY_THLD_INT_ST

This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value.
RESP_READY_INT_ST

This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value.
NXT_CMD_REQ_ERR_INT_ST

This interrupt is generated if toc is 0(master will restart next command), but command buf is empty.
TRANSFER_ERR_INT_ST

This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1’h1.
TRANSFER_COMPLETE_INT_ST

NA
COMMAND_DONE_INT_ST

NA
DETECT_START_INT_ST

NA
RESP_BUF_OVF_INT_ST

NA
IBI_DATA_BUF_OVF_INT_ST

NA
IBI_STATUS_BUF_OVF_INT_ST

NA
IBI_HANDLE_DONE_INT_ST

NA
IBI_DETECT_INT_ST

NA
CMD_CCC_MISMATCH_INT_ST

NA

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data